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High Performance Class-D Speaker Amplifier Series
17W+17W Class-D Speaker Amplifier for Analog Input
BD5423AEFS
No.09075EAT02
Overview BD5423AEFS is a 17W + 17W stereo class-D power amplifier IC, developed for space-saving and low heat-generation applications such as low-profile TV sets. The IC employs state-of-the-art Bipolar, CMOS, and DMOS (BCD) process technology that eliminates turn-on resistance in the output power stage and internal loss due to line resistances up to an ultimate level. With this technology, the IC has achieved high efficiency of 90% (10W + 10W output with 8 load), which is the top class in the industry. The IC, in addition, employs a compact back-surface heat radiation type power package to achieve low power consumption and low heat generation and eliminates necessity of installing an external radiator, up to a total output of 34W. This product satisfies both needs for drastic downsizing, low-profile structures and powerful, high-quality playback of the sound system. Features 1) A high efficiency of 90% (10W + 10W output with 8 load), which is the highest grade in the industry and low heat-generation. 2) An output of 17W + 17W (12V, with 4 load) is allowed without an external heat radiator. 3) Driving a lowest rating load of 4 is allowed. 4) Pop noise upon turning power on/off and power interruption has been reduced. 5) High-quality audio muting is implemented by soft-switching technology. 6) An output power limiter function limits excessive output to speakers. 7) High-reliability design provided with built-in protection circuits against high temperatures, against VCC shorting and GND shorting, against reduced-voltage, and against applying DC voltage to speaker. 8) A master/slave function allowing synchronization of multiple devices reduces beat noises. 9) Adjustment of internal PWM sampling clock frequencies (250kHz to 400kHz) allows easy protective measures against unwanted radio emission to AM radio band. 10) A compact back-surface heat radiation type power package is employed. HTSSOP-A44(5mm x 7.5mm x 1.0mm, pitch 0.8mm )
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1/17
2009.06 - Rev.A
BD5423AEFS
Technical Note
Absolute Maximum Ratings A circuit must be designed and evaluated not to exceed absolute maximum rating in any cases and even momentarily, to prevent reduction in functional performances and thermal destruction of a semiconductor product and secure useful life and reliability. The following values assume Ta =25. For latest values, refer to delivery specifications. Symbol Rating Unit Conditions Item Supply voltage Power dissipation Input voltage for signal pin Input voltage for control pin Input voltage for clock pin Operating temperature range Storage temperature range Maximum junction temperature VCC Pd VIN VCONT VOSC Topr Tstg Tjmax +20 2.0 4.5 -0.2 +7.2 -0.2 Vcc+0.2 -0.2 +7.2 -40 +85 -55 +150 +150 V W W V V V Pin 7, 8, 15, 16, 29, 30, 37, 38, 40 (Note 1, 2) (Note 3) (Note 4) Pin 1, 44 (Note 1) Pin 20, 24 (Note 1) Pin 23 (Note 1)
(Note 1) A voltage that can be applied with reference to GND (pins 11, 12, 33, 34, and 43) (Note 2) Pd and Tjmax=150 must not be exceeded. (Note 3) 70mm x 70mm x 1.6mm FR4 One-sided glass epoxy board (Back copper foil 0%) installed. If used under Ta=25 or higher, reduce 16mW for increase of every 1. The board is provided with thermal via. (Note 4) 70mm x 70mm x 1.6mm FR4 Both-sided glass epoxy board (Back copper foil 100%) installed. If used under Ta=25 or higher, reduce 36mW for increase of every 1. The board is provided with thermal via.
Operating Conditions The following values assume Ta =25. Check for latest values in delivery specifications. Symbol Rating Unit Conditions Item Supply voltage Load resistance
(Note 5) Pd should not be exceeded.
VCC RL
+10+16.5 4 16
V
Pin 7, 8, 15, 16, 29, 30, 37, 38, 40 (Note 5)
Electrical Characteristics Except otherwise specified Ta = 25, VCC = 12V, fIN = 1kHz, Rg = 0, RL = 8MUTEX="H", MS="L" For latest values, refer to delivery specifications. Representative Symbol Unit Conditions Item value Whole circuit Circuit current 1 (Sampling mode) Circuit current 2 (Muting mode) Control circuit "H" level input voltage "L" level input voltage Audio circuit Voltage gain Maximum output power 1 (Note 6) Maximum output power 2 (Note 6) Total harmonic distortion (Note 6) Crosstalk Output noise voltage (Sampling mode) Residual noise voltage (Muting mode) Internal sampling clock frequency GV PO1 PO2 THD CT VNO VNOM FOSC 28 10 17 0.1 85 80 1 250 dB W W % dB Vrms Vrms kHz PO = 1W THD+N = 10%, RL = 8 THD+N = 10%, RL = 4 PO = 1W, BW=20Hz20kHz PO = 1W, Rg = 0, BW = IHF-A Rg = 0, BW = IHF-A Rg = 0, BW = IHF-A, MUTEX = "L" MS = "L" (In master operation) VIH VIL 2.312 00.8 V V SDX, MUTEX, MS SDX, MUTEX, MS ICC1 ICC2 25 10 mA mA With no signal MUTEX = "L"
(Note 6) The rated values of items above indicate average performances of the device, which largely depend on circuit layouts, components, and power supplies. The reference values are those applicable to the device and components directly installed on a board specified by us.
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2/17
2009.06 - Rev.A
BD5423AEFS
Electrical characteristic curves (Reference data) (1) Under Stereo OperationRL=8
Technical Note
100 Vcc=12V RL=8 BW=2020kHz
THD+N (%)
100 Vcc=12V RL=8 Po=1W BW=2020kHz
10 THD+N (%)
10
1
6kHz
1
0.1
1kHz 100Hz
0.1
0.01 0.001
0.01
0.01
0.1 1 OUTPUT POWER (W)
10
100
10
100
1000 10000 FREQUENCY (Hz)
100000
Fig. 1 THD+N Output power
Fig. 2 THD+N Frequency
40 35 VOLTAGE GAIN (dB)
CROSSTALK (dB)
0 -20 Vcc=12V RL=8 Po=1W BW=2020kHz
30 25 20 15 10 5 0 10 100 1000 FREQUENCY (Hz) 10000 100000 Vcc=12V RL=8 Po=1W L=33H C=0.47F C=0.1F
-40 -60 -80 -100 10 100 1000
10000
100000
FREQUENCY (Hz)
Fig. 3 Voltage gain - Frequency
Fig. 4 Crosstalk - Frequency
0
OUTPUT POWER (W)
CROSSTALK (dB)
-20 -40 -60 -80 -100 0.001
Vcc=12V RL=8 fin=1kHz BW=2020kHz
20
RL=8 fin=1kHz
THD=10%
15 10 5 0 THD=1%
0.01
0.1
1
10
100
8
10
12
14
16
18
OUTPUT POWER (W)
Fig. 5 Crosstalk - Output power Fig. 6
VCC (V)
Output power - Power supply voltage
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3/17
2009.06 - Rev.A
BD5423AEFS
Electrical characteristic curves (Reference data) - Continued
Technical Note
100 90 80 70 60 50 40 30 20 10 0 0 5 10
Vcc=10V RL=8 fin=1kHz
100 90 80 70 60 50 40 30 20 10 0 0 5 10
EFFICIENCY (%)
EFFICIENCY (%)
Vcc=12V RL=8 fin=1kHz
15
20
15
20
OUTPUT POWER (W/ch)
Fig. 7 Efficiency - Output power
OUTPUT POWER (W/ch)
Fig. 8 Efficiency - Output power
100 90 80 70 60 50 40 30 20 10 0 0 5 10
3 Vcc=16.5V Vcc=12V 2 ICC (A) Vcc=10V 1
Vcc=16.5V RL=8 fin=1kHz RL=8 fin=1kHz
EFFICIENCY (%)
0 15 20 0 5 10 15 20 25 30 35 40 OUTPUT POWER (W/ch)
Fig. 9 Efficiency - Output power
TOTAL OUTPUT POWER (W)
Fig. 10 Current consumption - Output power
100 90 80 70 60 50 40 30 20 10 0 8
0
RL=8 RL=8 Without signal
-20 NOISE FFT (dBV) -40 -60 -80 -100 -120 -140 10 100
Vcc =12V Vcc=12V RL=8 RL=8
Without signal BW=2020kHz BW=20 20kHz
ICC (mA)
Sampling Mute
Without
10
12
14 VCC (V)
16
18
1000
10000
100000
FREQUENCY (Hz)
Fig. 12 FFT of Output Noise Voltage
Fig. 11 Current consumption - Power supply voltage
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4/17
2009.06 - Rev.A
BD5423AEFS
Electrical characteristic curves (Reference data) - Continued
Technical Note
MUTEX Pin 20
10V/div
TM Pin 26
5V/div
Vcc=12V MUTEX Pin 20 RL =8 Po=500mW fin=500Hz TM Pin 26
10V/div
5V/div
Vcc=12V RL =8 Po=500mW fin=500Hz
Speaker Output
2V/div 10msec/div
Speaker Output
2V/div
10msec/div
Fig. 13 Wave form when Releasing Soft-mute
Fig. 14 Wave form when Activating Soft-mute
VCCA VHOLD Pin 27 TM Pin 26 5V/div
VCCA VHOLD Vcc=12V Pin 27 RL =8 Po=500m W TM fin=3kHz Pin 26 5V/div Vcc=12V RL =8 Po=500m W fin=3kHz
5V/div
5V/div
Speaker Output
2V/div Speaker Output 20msec/div 2msec/div
2V/div
Fig. 15 Wave form on Instantaneous Power Interruption (20msec / div)
Fig. 16 Wave form on Instantaneous Power Interruption (2msec / div)
Soft Clip
5V/div
Speaker Output Soft Clip 200sec/div
Vcc=12V RL =8 Po=5W THD+n=10% fin=1kHz R2=91k R3=22k
Fig. 17 Wave form on Output Power Limiter function (Po = 5W)
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5/17
2009.06 - Rev.A
BD5423AEFS
Electrical characteristic curves (Reference data) - Continued (2)Under Stereo OperationRL=6
Technical Note
25 OUTPUT POWER (W) 20 15 10 5 0 8 10 12 14 16 18 VCC (V)
Fig. 18 Output power - Power supply voltage
RL=6 fin=1kHz
THD=10%
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15
Vcc=10V RL=6 fin=1kHz
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15
EFFICIENCY (%)
EFFICIENCY (%)
Vcc=12V RL=6 fin=1kHz
20
25
20
25
OUTPUT POWER (W/ch)
Fig. 19 Efficiency - Output power
OUTPUT POWER (W/ch)
Fig. 20 Efficiency - Output power
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15
4 Vcc=16.5V 3 ICC (A) Vcc=10V 2 1 0 0 5 10 15 20 25 30 35 40 45 50 TOTAL OUTPUT POWER (W)
Fig. 22 Current consumption - Output power
EFFICIENCY (%)
Vcc=12V
Vcc=16.5V RL=6 fin=1kHz
RL=6 fin=1kHz
20
25
OUTPUT POWER (W/ch)
Fig. 21 Efficiency - Output power
Dotted lines of the graphs indicate continuous output power to be obtained on musical signal source or by installing additional heat sinks.
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6/17
2009.06 - Rev.A
BD5423AEFS
Electrical characteristic curves (Reference data) - Continued (3) Under Stereo OperationRL=4
Technical Note
30 OUTPUT POWER (W) 25 20 15 10 5 0 8 10 12 14 16 18 VCC (V)
Fig. 23 Output power - Power supply voltage
RL=4 fin=1kHz
THD=10%
100 90 80 70 60 50 40 30 20 10 0 0 5 10
Vcc=10V RL=4 fin=1kHz
100 90 80 70 60 50 40 30 20 10 0 0 5 10
EFFICIENCY (%)
EFFICIENCY (%)
Vcc=12V RL=4 fin=1kHz
15
20
15
20
OUTPUT POWER (W/ch)
Fig. 24 Efficiency - Output power
OUTPUT POWER (W/ch)
Fig. 25 Efficiency - Output power
100 90 80 70 60 50 40 30 20 10 0 0 5 10
4 Vcc=12V 3 ICC (A) 2 1 0 15 20 0 5 10 15 20 25 30 35 40 OUTPUT POWER (W/ch)
Fig. 26 Efficiency - Output power
Vcc=10V
EFFICIENCY (%)
Vcc=16.5V
RL=4 fin=1kHz
Vcc=16.5V RL=4 fin=1kHz
TOTAL OUTPUT POWER (W)
Fig. 27 Current consumption - Output power
Dotted lines of the graphs indicate continuous output power to be obtained on musical signal source or by installing additional heat sinks.
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7/17
2009.06 - Rev.A
BD5423AEFS
Pin Assignment
Outer Dimensions and Inscriptions
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IN1 1 2 GNDA 3 FIL A PW M 1 PW M 2 V CCA FILP 4 5 6 7 8 9 DRI VER 1P 10 11 12 13 14 15 16 17 18 W ARNING ERROR M UTEX 19 20 W ARNING ERROR M ute Control N.C. 21 N.C. N.C. 22 N.C. Protections & Logi c Under V ol tage Protection High Temperature Protection Power-off Detector Soft M ute Ramp Generator Output Short Protection Output DC V ol tage Protection Clock Control 44 IN2 43 GNDA 42 FIL A 41 FIL P 40 V CCA 39 BSP2P 38 V CCP2P 37 V CCP2P 36 OU T2P DRI VER 2P 35 OU T2P 34 GNDP2 33 GNDP2 32 OU T2N DRI VER 1N DRI VER 2N 31 OU T2N 30 V CCP2N 29 V CCP2N 28 BSP2N 27 VHOLD 26 TM 25 ROSC 24 M S PLM T1 PLM T2 PLM T3 PLM T4 BSP1P V CCP1P V CCP1P OUT1P OUT1P GNDP1 GNDP1 OUT1N OUT1N V CCP1N V CCP1N BSP1N
Power L imi t
(c) 2009 ROHM Co., Ltd. All rights reserved.
BD5423AEFS
Top View
Fig. 28 Pin Assignment Diagram
Fig. 29 Outer Dimensions and Inscriptions of HTSSOP-A44 Package
8/17 Type
Lot No.
2009.06 - Rev.A
Technical Note
23 OSC
BD5423AEFS
Explanation of Pin Functions (Provided pin voltages are typical values.) No. Symbol Pin voltage Pin description
Technical Note
Internal equalizing circuit
1 44
IN1 IN2
3.5V
ch1 Analog signal input pin ch2 Analog signal input pin Input audio signal via a capacitor.
2
PLMT1
3.5V
Voltage-to-current conversion pin for output power limiter function Connect a register.
3
PLMT2
-
Current-to-voltage conversion pin for output power limiter function Connect a register.
4
PLMT3
-
Current-to-voltage conversion pin for output power limiter function Connect a register.
Bias pin for output power limiter function 5 PLMT4 3.5V Connect a register and a capacitor.
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9/17
2009.06 - Rev.A
BD5423AEFS
Explanation of Pin Functions (continued) No. Symbol Pin voltage 6 BSP1P -
Technical Note
Pin description
Internal equalizing circuit
ch1 positive bootstrap pin Connect a capacitor.
7, 8
VCCP1P
Vcc
ch1 positive power system power supply pin
9, 10
OUT1P
Vcc0V
ch1 positive PWM signal output pin Connect with output LPF.
11, 12
GNDP1
0V
ch1 power system GND pin
13, 14
OUT1N
Vcc0V
ch1 negative PWM signal output pin Connect with output LPF.
15, 16
VCCP1N
Vcc
ch1 negative power system power supply pin
17
BSP1N
-
ch1 negative bootstrap pin Connect a capacitor.
Warning output pin H: 5V L: 0V Pin to notify operation warning. H: Under warning L: Normal operation Connect a resister.
18
WARNING
Error output pin H: 5V L: 0V A pin for notifying operation errors. H: Error L: Normal operation Connect a resister.
19
ERROR
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10/17
2009.06 - Rev.A
BD5423AEFS
Explanation of Pin Functions (continued) No. Symbol Pin voltage
Technical Note
Pin description
Internal equalizing circuit
Audio mute control pin 20 MUTEX H: Mute off L: Mute on
21, 22
N.C.
-
N.C. pin Nothing is connected with IC internal circuit.
Sampling clock signal input/output pin 23 OSC When using two or more sampling clocks, connect via a capacitor.
Master/Slave switching pin 24 MS Switching of master/slave functions on a sampling clock signal. H: Slave operation L: Master operation
25
ROSC
5.6V
Internal PWM sampling clock frequency setting pin Usually the pin is used open. To adjust an internal sampling clock frequency, connect a resister.
Audio muting constant setting pin 26 TM 05V Connect a capacitor.
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11/17
2009.06 - Rev.A
BD5423AEFS
Explanation of Pin Functions (continued) No. Symbol Pin voltage
Technical Note
Pin description
Internal equalizing circuit
Instantaneous power interruption detecting voltage setting pin 27 VHOLD 0.68xVcc Connect a capacitor. To adjust a detecting voltage, connect a resister.
28
BSP2N
-
ch2 negative bootstrap pin Connect a capacitor.
29, 30
VCCP2N
Vcc
ch2 negative power system power supply pin
31, 32
OUT2N
Vcc0V
ch2 negative PWM signal output pin Connect an output LPF.
33, 34
GNDP2
0V
ch2 power system GND pin
35, 36
OUT2P
Vcc0V
ch2 positive PWM signal output pin Connect an output LPF.
37, 38
VCCP2P
Vcc
ch2 positive power system power supply pin
39
BSP2P
-
ch2 positive bootstrap pin Connect a capacitor.
40
VCCA
Vcc
Analog system power pin
41
FILP
Vcc+35 12
PWM system bias pin Connect a capacitor.
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12/17
2009.06 - Rev.A
BD5423AEFS
Explanation of Pin Functions (continued) No. Symbol Pin voltage
Technical Note
Pin description
Internal equalizing circuit
Analog signal system bias pin 42 FILA 3.5V Connect a capacitor.
43
GNDA
0V
Analog system power supply pin
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13/17
2009.06 - Rev.A
C1 2.2F C44 2.2F R2 22k 1 43 GN DA 44 I NP UT ch-2
BD5423AEFS
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I NP UT ch-1
Vcc=10V16.5V
GNDA
2 3 FILA
GNDA
P wer o
42
C 42 10F
C43 10F
R3 22k C 41 1F
4
Limit
P W M1 VCCA P W M2 FI LP 41
R4
C 40 0.1F
C 5 0.1F 22k VCCA
5 6 39 VCCP 40
Application Circuit Diagram.
GNDA
V CCP 7 8 37 38
(c) 2009 ROHM Co., Ltd. All rights reserved.
C 39 0.68F C6 0.68F C38 10F C 7 0.1F C 37 0.1F C8 10F
L9 15 H 9 36 35 34 33 GN DP 13 32 31 30 29 28 WA RNI N G ER ROR P rotecti on s & Logi c Po wer-off Detector Soft Mute 27 26 R amp Generator Output Short Prot ection Output DC Volt age Prot ection N.C. 22 N. C. 25 24 Clock Control MASTER 23 C23 0.1F CLK I/O C26 0.1F OPEN SL AVE L31 15 H L35 15 H
DRI VER 1P
DRI VER 2P
10 11 12 GN DP
C35
0.22F
C 9 0.22F
SP ch1
SP ch2 4
C 32 1F
C10 1F
0.22F
C13 0.22F
4
C31
Fig. 30 Circuit diagram under stereo operation with 4- load
14/17
DRI VER 1N DRI VER 2N
L13 15 H 14 15 16 17 18 R18 100k 19 20 Control N.C. 21 N. C. Mute R19 100k MUTE
C15 0.1F C17 0.68F
Und er Vol tag e Protection High Temperature Protection
C29 0.1F C28 0.68F
GNDD
W A RNI N G OUTP UT
C27 3.3F
ER ROR OUTP UT
2009.06 - Rev.A
Technical Note
BD5423AEFS
Table 1 BOM list for stereo operation with 4- load
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 No. 14 Item IC C C C C C C C C C C R R Item L Part Number BD5423AEFS GRM219B31E684KA88D GRM188R11H104KA93 GRM31MB11H224KA01 25ST225M3216 50ST105M3225 GRM21BB31E335KA75 GRM188B11E104KA GRM21BB11C105KA GRM21BB31C106KE15 25SVPD10M MCR01MZPF2202 MCR01MZPF1003 Part Number 7G09B-150M Vendor ROHM Configuration mm inch 0805 0603 1206 1210 1210 0805 0603 0805 0805 2626 0402 0402
HTSSOP-A44
Technical Note
Value 0.68F 0.1F 0.22F 2.2F 1F 3.3F 0.1F 1F 10F 10F 22k 100k Value 15Hx2
Rated voltage 25V 50V 50V 25V 50V 25V 25V 16V 16V 25V 50V 50V Tolerance 20%
Tolerance 10% 10% 10% 20% 20% 10% 10% 10% 10% 20% 1% 1% DC Resistance 44mmax.
Temperature characteristics 10% 10% 10% 5% 5% 10% 10% 10% 10% 25% 200ppm/C 200ppm/C Rated DC Current 4.1A max.
Quantity 1 4 5 4 2 2 1 3 1 1 3 3 2 Quantity 2 IC1
Reference
MURATA 2012 MURATA 1608 MURATA 3216 Rubycon Rubycon 3225 3225
C6, C17, C28, C39 C7, C15, C29, C37, C40 C9, C13, C31, C35 C1, C44 C10, C32 C27 C5, C23, C26 C41 C42 C8, C38, C43 R2, R3, R4 R18, R19 Reference L9, L13, L31, L35
MURATA 2012 MURATA 1608 MURATA 2012 MURATA 2012 SANYO ROHM ROHM Vendor SAGAMI 6666 1005 1005
Configuration mm 10x9x10
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15/17
2009.06 - Rev.A
BD5423AEFS
Technical Note
Notes for use Notes for use 1. About absolute maximum ratings If an applied voltage or an operating temperature exceeds an absolute maximum rating, it may cause destruction of a device. A result of destruction, whether it is short mode or open mode, is not predictable. Therefore, provide a physical safety measure such as fuse, against a special mode that may violate conditions of absolute maximum ratings. 2. About power supply line As return of current regenerated by back EMF of output coil happens, take steps such as putting capacitor between power supply and GND as a electric pathway for the regenerated current. Be sure that there is no problem with each property such as emptied capacity at lower temperature regarding electrolytic capacitor to decide capacity value. If the connected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute maximum ratings. It is recommended to implement a physical safety measure such as the insertion of a voltage clamp diode between the power supply and GND pins. 3. Potential of GND (11, 12, 33, 34, and 43 pins) Potential of the GND terminal must be the lowest under any operating conditions. 4. About thermal design Perform thermal design with sufficient margins, in consideration of maximum power dissipation Pd under actual operating conditions. This product has an exposed frame on the back of the package, and it is assumed that the frame is used with measures to improve efficiency of heat dissipation. In addition to front surface of board, provide a heat dissipation pattern as widely as possible on the back also. A class-D power amplifier has heat dissipation efficiency far higher than that of conventional analog power amplifier and generates less heat. However, extra attention must be paid in thermal design so that a power dissipation Pdiss should not exceed the maximum power dissipation Pd. Tjmax - Ta Tjmax: Maximum temperature junction = 150[] W Pd Maximum power dissipation Ta: Operating ambient temperature [] ja ja: Package thermal resistance [/W] 1 Po: Output power [W] Pdiss PO - 1 W Power dissipation : Efficiency 5. About operations in strong electric field Note that the device may malfunction in a strong electric field. 6. Thermal shutdown (TSD) circuit This product is provided with a built-in thermal shutdown circuit. When the thermal shutdown circuit operates, the output transistors are placed under open status. The thermal shutdown circuit is primarily intended to shut down the IC avoiding thermal runaway under abnormal conditions with a chip temperature exceeding Tjmax = 150, and is not intended to protect and secure an electrical appliance. Accordingly, do not use this circuit function to protect a customer's electrical appliance. 7. About shorting between pins and installation failure Be careful about direction and displacement of an LSI when installing it onto the board. Faulty installation may destroy the LSI when the device is energized. In addition, a foreign matter getting in between LSI pins, pins and power supply, and pins and GND may cause shorting and destruction of the LSI. 8. About power supply startup and shutdown When starting up a power supply, be sure to place the MUTEX pin (pin 20) at "L" level. When shutting down a power supply also, be sure to place the pin at "L" level. Those processes reduce pop noises generated upon turning on and off the power supply. In addition, all power supply pins must be started up and shut down at the same time. 9. About WARNING output pin (pin 18) and ERROR output pin (pin 19) A WARNING flag is output from the WARNING output pin upon operation of the high-temperature protection function and under-voltage protection function. And an ERROR flag is output from the ERROR output pin upon operation of VCC/GND shorting protection function and speaker DC voltage applying protection function. These flags are the function which the condition of this product is shown in. The use which aimed at the protection except for this product is prohibition. 10. About N.C. pins (pins 21 and 22) The N.C. (Non connection) pins are not connected with an internal circuit. Leave the pins open or connect them to GND.
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16/17
2009.06 - Rev.A
BD5423AEFS
Ordering part number
Technical Note
B
Part No BD.
D
5
Part No. 5423A
4
2
3
A
E
F
S
-
E
2
Package EFS:HTSSOP-44
Packaging and forming specification E2: Embossed tape and reel
HTSSOP-A44
18.50.1 (MAX 18.85 include BURR) (6.0)
44 23

+6 4 -4
Tape Quantity
1.00.2
Embossed carrier tape (with dry pack) 1500pcs E2
The direction is the 1pin of product is at the upper left when you hold
9.50.2
7.50.1
0.50.15
Direction of feed
(5.0)
( reel on the left hand and you pull out the tape on the right hand
)
1
0.85
1PIN MARK
22
+0.05 0.17 -0.03 S
1.0MAX
0.08 S
0.850.05
0.080.05
0.8
+0.05 0.37 -0.04
0.08
M
1pin (Unit : mm) Reel
Direction of feed
Order quantity needs to be multiple of the minimum quantity.
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17/17
2009.06 - Rev.A
Notice
Notes
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